Video

mipi_dsi: dsi@4acf0000 {
	compatible = "nxp,imx95-mipi-dsi";
	reg = <0x0 0x4acf0000 0x0 0x10000>;
	interrupt-parent = <&displaymix_irqsteer>;
	interrupts = <48>;
	clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>,
		 <&scmi_clk IMX95_CLK_MIPIPHYPLLBYPASS>,
		 <&scmi_clk IMX95_CLK_MIPIPHYPLLREF>,
		 <&scmi_clk IMX95_CLK_CAMAPB>,
		 <&scmi_clk IMX95_CLK_DISP1PIX>;
	clock-names = "cfg", "bypass", "ref", "pclk", "pix";
	assigned-clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>,
			  <&scmi_clk IMX95_CLK_MIPIPHYPLLBYPASS>,
			  <&scmi_clk IMX95_CLK_MIPIPHYPLLREF>;
	assigned-clock-parents = <&scmi_clk IMX95_CLK_24M>,
				 <&scmi_clk IMX95_CLK_VIDEOPLL1>,
				 <&scmi_clk IMX95_CLK_24M>;
	mux-controls = <&mux 0>;
	power-domains = <&scmi_devpd IMX95_PD_CAMERA>;
	nxp,disp-master-csr = <&display_master_csr>;
	nxp,disp-stream-csr = <&display_stream_csr>;
	nxp,mipi-combo-phy-csr = <&mipi_tx_phy_csr>;
	status = "disabled";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			mipi_dsi_to_display_pixel_link0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&display_pixel_link0_to_mipi_dsi>;
			};

			mipi_dsi_to_display_pixel_link1: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&display_pixel_link1_to_mipi_dsi>;
			};
		};

		port@1 {
			reg = <1>;
		};
	};
};

dpu: display-controller@4b400000 {
	compatible = "nxp,imx95-dpu";
	[...]
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			dpu_disp0_to_pixel_interleaver_disp0: endpoint {
				remote-endpoint = <&pixel_interleaver_disp0_to_dpu_disp0>;
			};
		};

		port@1 {
			reg = <1>;

			dpu_disp1_to_pixel_interleaver_disp1: endpoint {
				remote-endpoint = <&pixel_interleaver_disp1_to_dpu_disp1>;
			};
		};
	};
};

ldb: ldb@4 {
	compatible = "fsl,imx95-ldb";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x4 0x4>;
	clocks = <&lvds_csr IMX95_CLK_DISPMIX_PIX_DI0_GATE>,
		 <&lvds_csr IMX95_CLK_DISPMIX_PIX_DI1_GATE>,
		 <&lvds_csr IMX95_CLK_DISPMIX_LVDS_CH0_GATE>,
		 <&lvds_csr IMX95_CLK_DISPMIX_LVDS_CH1_GATE>;
	clock-names = "ldb_di0", "ldb_di1", "ldb_ch0", "ldb_ch1";
	status = "disabled";

	channel@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;
		phys = <&ldb0_phy1>;
		phy-names = "lvds_phy";
		status = "disabled";

		port@0 {
			reg = <0>;

			ldb_ch0_to_display_pixel_link0: endpoint {
				remote-endpoint = <&display_pixel_link0_to_ldb_ch0>;
			};
		};

		port@1 {
			reg = <1>;
		};
	};

	channel@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <1>;
		phys = <&ldb1_phy1>;
		phy-names = "lvds_phy";
		status = "disabled";

		port@0 {
			reg = <0>;

			ldb_ch1_to_display_pixel_link1: endpoint {
				remote-endpoint = <&display_pixel_link1_to_ldb_ch1>;
			};
		};

		port@1 {
			reg = <1>;
		};
	};
};

ldb0_phy: phy@8 {
	compatible = "fsl,imx95-lvds0-phy";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x8 0x4>;
	gpr = <&lvds_csr>;
	clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
	clock-names = "apb";
	power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
	status = "disabled";

	ldb0_phy1: port@0 {
		reg = <0>;
		#phy-cells = <0>;
	};
};

ldb1_phy: phy@c {
	compatible = "fsl,imx95-lvds1-phy";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xc 0x4>;
	gpr = <&lvds_csr>;
	clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
	clock-names = "apb";
	power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
	status = "disabled";

	ldb1_phy1: port@0 {
		reg = <0>;
		#phy-cells = <0>;
	};
};