PCI Express is a third-generation I/O interconnect targeting low-cost, high-volume, multi-platform interconnection. The NXP i.MX95 CPU has two independent PCI Express (PCIe) controllers, each supporting a single-lane link up to Gen 3 speeds.

The BSP configures the PCIe port 0 to act as Root Complex (RC).

On the ConnectCore 95 SMT SOM:

  • The PCIe buses are available on the LGA pads.

On the ConnectCore 95 SMARC SOM:

  • PCIE1 is routed to PCIE_A on the SMARC connector.

  • PCIE2 is routed to PCIE_B on the SMARC connector.

On the ConnectCore 95 Development Kit:

  • PCIE1 is routed to the M.2 E-Key connector.

  • PCIE2 is routed to the M.2 B-Key connector.

In hardware version 2 of the SMARC SOM, PCIE1 clock differential lines are swapped compared to the SMARC definition:

  • PCIE1_CLKOUT_N is connected to SMARC pad P84 (PCIE_A_REFCK+)

  • PCIE1_CLKOUT_P is connected to SMARC pad P85 (PCIE_A_REFCK-)

This issue has been fixed on hardware version 3 of the SMARC SOM and the ConnectCore 95 Development Kit.

Kernel configuration

You can manage the PCIe driver support through the kernel configuration option:

  • Freescale i.MX6/7/8 PCIe controller (CONFIG_PCI_IMX6)

This option is enabled as built-in on the default ConnectCore 95 kernel configuration file.

Kernel driver

The PCIe bus driver for the ConnectCore 95 system-on-module is located at drivers/pci/controller/dwc/pci-imx6.c.

Device tree bindings and customization

The i.MX95 PCIe interface device tree binding is documented at Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml.

Example: PCIE1 on M.2 E-Key connector on the ConnectCore 95 Development Kit

Definition of the PCIe bus

i.MX95 device tree
		pcie0: pcie@4c300000 {
			compatible = "fsl,imx95-pcie";
			reg = <0 0x4c300000 0 0x10000>,
			      <0 0x4c360000 0 0x20000>,
			      <0 0x60100000 0 0xfe00000>;
			reg-names = "dbi", "atu", "config";
			[...]
			status = "disabled";
		};

		serdes0_ssr: ssr@4c340000 {
			compatible = "fsl,imx95-serdes-syscfg", "syscon";
			reg = <0 0x4c340000 0 0x2000>;
		};

		pcie1: pcie@4c380000 {
			compatible = "fsl,imx95-pcie";
			reg = <0 0x4c380000 0 0x10000>,
			      <0 0x4c3e0000 0 0x20000>,
			      <8 0x80100000 0 0xfe00000>;
			reg-names = "dbi", "atu", "config";
			[...]
			status = "disabled";
		};

		pcie1_ep: pcie-ep@4c380000 {
			compatible = "fsl,imx95-pcie-ep";
			reg = <0 0x4c380000 0 0x10000>,
			      <0 0x4c3a0000 0 0x1000>,
			      <0 0x4c3e0000 0 0x1000>,
			      <0 0x4c3f0000 0 0x10000>,
			      <0xa 0 1 0>;
			reg-names = "dbi", "dbi2", "atu", "dma", "addr_space";
			[...]
			status = "disabled";
		};

		serdes1_ssr: ssr@4c3c0000 {
			compatible = "fsl,imx95-serdes-syscfg", "syscon";
			reg = <0 0x4c3c0000 0 0x2000>;
		};

PCIe port on the ConnectCore 95 Development Kit

Combined device tree of SMARC SOM and DVK
&pcie0 {
	vpcie-supply = <&reg_3v3_board>;
	reset-gpios = <&mca_gpio 25 GPIO_ACTIVE_LOW>;   /* MCA PB10 */
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
	status = "okay";
};