The NXP i.MX95 CPU has one 10 Gigabit Ethernet MAC and two 10/100/1000 Ethernet MAC.

On the ConnectCore 95 SMT SOM:

  • Ethernet 1G port 1 is routed to the castellated pads.

  • All three Ethernet ports are routed to the LGA pads.

On the ConnectCore 95 SMARC SOM:

  • Ethernet port 1 is connected to a 10/100/1000 Microchip Technology LAN8840 PHY and routed to GBE0 port of the SMARC connector.

  • Ethernet port 2 is connected to a 10/100/1000 Microchip Technology LAN8840 PHY and routed to GBE1 port of the SMARC connector.

On the ConnectCore 95 Development Kit:

  • Ethernet ports GBE0 and GBE1 are routed to RJ45 connectors.

  • Ethernet 10Gbit port is not yet supported on the ConnectCore 95 Development Kit.

Kernel configuration

You can manage the Ethernet driver and PHY Device support through the following kernel configuration options:

  • ENETC PF driver (FSL_ENETC)

  • ENETC4 PF driver (FSL_ENETC4)

  • ENETC VF driver (FSL_ENETC_VF)

  • Microchip PHYs (CONFIG_MICROCHIP_PHY)

These options are enabled as built-in on the default ConnectCore 95 kernel configuration file.

Kernel driver

The drivers for the Ethernet interface are located at:

File Description

drivers/net/ethernet/freescale/enetc/enetc4_pf.c

ENETC4 PF driver

drivers/net/phy/microchip.c

Microchip PHYs

Device tree bindings and customization

The i.MX95 Ethernet interface device tree binding is documented at Documentation/devicetree/bindings/net/fsl,netc.yaml. The Ethernet interface is defined in the i.MX95 CPU and ConnectCore 95 Development Kit device tree files.

Definition of the Ethernet interfaces

i.MX95 device tree
	pcie_4ca00000: pcie@4ca00000 {

		[...]

		enetc_port0: ethernet@0,0 {
			compatible = "fsl,imx95-enetc";
			reg = <0x000000 0 0 0 0>;
			clocks = <&scmi_clk IMX95_CLK_ENETREF>;
			clock-names = "enet_ref_clk";
			nvmem-cells = <&eth_mac0>;
			nvmem-cell-names = "mac-address";
			status = "disabled";
		};

		enetc_port1: ethernet@8,0 {
			compatible = "fsl,imx95-enetc";
			reg = <0x004000 0 0 0 0>;
			clocks = <&scmi_clk IMX95_CLK_ENETREF>;
			clock-names = "enet_ref_clk";
			nvmem-cells = <&eth_mac1>;
			nvmem-cell-names = "mac-address";
			status = "disabled";
		};

		enetc_port2: ethernet@10,0 {
			compatible = "fsl,imx95-enetc";
			reg = <0x008000 0 0 0 0>;
			nvmem-cells = <&eth_mac2>;
			nvmem-cell-names = "mac-address";
			status = "disabled";
		};

		[...]
	};

Enable Ethernet ports and PHYs

ConnectCore 95 SMARC SOM:
/ {
	aliases {
		ethernet0 = &enetc_port0;
		ethernet1 = &enetc_port1;
	};
};

&enetc_port0 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enetc0>;
	pinctrl-1 = <&pinctrl_enetc0_sleep>;
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
	status = "okay";
};

&enetc_port1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enetc1>;
	pinctrl-1 = <&pinctrl_enetc1_sleep>;
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii-id";
	status = "okay";
};

&netc_emdio {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emdio>;
	status = "okay";

	ethphy0: ethernet-phy@5 {
		reg = <5>;
		compatible = "ethernet-phy-ieee802.3-c22";
		status = "okay";
	};

	ethphy1: ethernet-phy@7 {
		reg = <7>;
		compatible = "ethernet-phy-ieee802.3-c22";
		status = "okay";
	};
};

IOMUX configuration

ConnectCore 95 Development Kit device tree
&scmi_iomuxc {

	[...]

	pinctrl_emdio: emdiogrp{
		fsl,pins = <
			IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x57e
			IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x97e
		>;
	};

	[...]

	pinctrl_enetc0: enetc0grp {
		fsl,pins = <
			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x57e
			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x57e
			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x57e
			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x57e
			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e
			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e
			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e
			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e
			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e
			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e
			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e
			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e
		>;
	};

	pinctrl_enetc0_sleep: enetc0grp-sleep {
		fsl,pins = <
			IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2		0x200
			IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3		0x200
			IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4		0x200
			IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5		0x200
			IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6		0x200
			IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7		0x200
			IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8		0x200
			IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9		0x200
			IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10		0x200
			IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11		0x200
			IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12		0x200
			IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13		0x200
		>;
	};

	[...]
};

MAC addresses

The MAC addresses of the i.MX95 Ethernet interfaces are programmed in the U-Boot environment (variables ethaddr, eth1addr, and eth2addr) on the ConnectCore 95 eMMC. The MAC address of the first Ethernet interface is also printed on the module label. U-Boot writes the MAC addresses in the ethaddr, eth1addr, and eth2addr environment variables into their respective device tree nodes under the local-mac-address property. For more information, see Environment variables.

Ethernet user space usage

In the Linux system, the Ethernet interface is known as ethX where X is a number, starting at 0, that indicates the interface index. The Ethernet driver exposes device data through the sysfs at /sys/class/net/ethX. You can use NetworkManager to configure Ethernet settings such as IP and netmask.