Features and functionality

The ConnectCore 93 system-on-module is based on thei.MX 93 processor from NXP. This processor offers a number of interfaces, most of them multiplexed and not available simultaneously. The module has the following features:

Single/Dual Cortex-A55 MPCore platform:
- Frequency operating at up to 1.7 GHz.
- 32 KB L1 instruction cache.
- 32 KB L1 data cache.
- 64 KB per-core L2 cache.
- Media Processing Engine (MPE) with ARM NEON technology supporting the Advanced Single Instruction Multiple Data architecture.
- Floating Point Unit (FPU) with support of the Arm VFPv4-D16 architecture.
- Support of 64-bit Arm v8.2-A architecture.
- 256 KB cluster L3 cache.
- Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs.
- Boot ROM (256 KB).
- On-chip RAM (640 KB).
- Security:
  - Trusted resource domain controller (TRDC).
  - ARM TrustZone (TZ) architecture, including both Trustzone-A and Trustzone-M.
  - On-chip RAM (OCRAM) secure region protection using OCRAM controller.
  - EdgeLock secure enclave.
  - Battery backed security module (BBSM):
    - Secure non-volatile storage (SNVS).
    - Secure real-time clock (RTC).
Cortex-M33 core platform:
- Frequency operating up to 250 MHz.
- Support FPU, MPU, NVIC, FPB, DWT and ITM.
- Two-way set-associative 16 KB system cache with parity support.
- Two-way set-associative 16 KB code cache with parity support.
- Boot ROM (256 KB).
Neural processing unit (NPU):
- NPU targets 8-bit and 16-bit integer RNN.
- Handles 8-bit weights.
System debug:
- Arm CoreSight debug and trace technology.
- Embedded trace FIFO (ETF) with 4 KB internal storage to provide trace buffering.
- Unified trace capability for dual core Cortex-A55 and Cortex-M33.
- Cross Triggering Interface (CTI).
- 5-pin JTAG.
Image sensor interface (ISI):
- Standard pixel formats commonly used in many camera input protocols.
- Programmable resolutions up to 2K.
- Image processing for:
  - Supports one source of up to 2K horizontal resolution.
  - Supports pixel rate up to 200 Mpixel/s.
- Image down scaling via decimation and bi-phase filtering.
- Color space conversion.
- Interlaced to progressive conversions.
Connectivity:
- x2 USB 2.0 controllers and PHYs interfaces.
- x2 CAN/CAN-FD.
- x2 I3C.
- x2 32-pin FlexIO modules.
- x3 uSDHC.
- x2 Ethernet controllers:
  - x1 Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), Ethernet AVB and IEEE 1588.
  - x1 Gigabit Ethernet controller with support for TSN in addition to EEE, Ethernet AVB and IEEE 1588.
- x8 LPSPI.
- x8 I2C.
- x8 LPUART.
Multimedia:
- LCDIF display controller, which can drive any of two displays:
  - MIPI DSI: up to 1920x1200p60.
  - LVDS Tx: up to 1366x768p60 or 1280x800p60.
- 2-lane MIPI CSI-2 interface:
  - Compliant with MIPI CSI-2 specification v1.2 and MIPI D-PHY specification v1.2.
  - Support up to 2 Rx data lanes (plus 1 Rx clock lane).
  - Support 80 Mbps - 1.5 Gbps per lane data rate in high speed operation.
  - Support 10 Mbps data rate in low power operation.
- 4-lane MIPI DSI display with data supplied by the LCDIF:
  - Compliant with MPI DSI specification v1.2 and MIPI D-PHY specification v1.2.
  - Capable of resolutions achievable with a 200 MHz pixel clock and active pixel rate of 140 Mpixel/s with 24-bit RGB.
  - Support 80 Mbps - 1.5 Gbps data rate per lane in high speed operation.
  - Support 10 Mbps data rate in low power operation.
- Audio:
  - x3 SAI interfaces:
    - SAI1 supports 2-lane and SAI3 supports 1 lane.
    - SAI2 supports 4 lanes.
    - SAI2 and SAI3 support glue-less switching between PCM and stereo DSD operation.
    - x1 SPDIF.
    - 24-bit PDM supports up to 8-microphones (4 lanes).
Up to 1 GB, 16-bit LPDDR4 memory.
Up to 8 GB, 8-bit eMMC memory.
NXP PCA9451 Power Management IC (PMIC):
- x6 Step down regulators.
- x5 Linear regulators.
- x1 Load switch.
IEEE 802.11 a/b/g/n/ac/ax WLAN interface.
Bluetooth version 5.4.